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Kevin Delmas
Biography and Research interests
Kevin Delmas -- Reasearch engineer ONERA/DTIS |
Short Biography
After an electronic and automation education, I obtained an engineer graduation in Automation and Electronic with a specialization in safety critical embedded systems at INSA Toulouse. I pursued a PhD at ONERA Toulouse focused on the application of SAT and SMT to safety assessment and safe architecture synthesis with Claire Pagetti and Remi Delmas. Since then, I am working as a research engineer at the ONERA Toulouse lab, my main research topics are:
- the use of formal methods to assist design and certification of embedded systems
- safety assessment methodologies for autonomous systems
- the development of model-based safety assessment methods and tools
- safety-driven architecture optimization relying on IA based methods
Research
Safety assessment and certification of embedded and autonomous systems
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Projects
- PHYLOG 2 (2021-2023) Certifiability (AMC 20-193 and security ED-202/ED-203) of hybrid multi-core architectures (i.e. heterogeneous multi-core with accelerators
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ANITI chair (2019 - 2023) : CertifAI -- towards AI-based applications certification.
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With my colleagues Mohammed Belcaid, Thomas Carle, Claire Pagetti, Mélanie Ducoffe, Adrien Gauffriau, Charles Lesire-Cabaniols, Jérémie Guiochet,
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Member of the mission DEEL Certif
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PHYDIAS 2 (2022-2025), PHYDIAS
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Certifiability of computer vision based systems for civil aeronautics
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Model-based safety assessments using formal methods for Unmanned Aerial Systems (UAS)
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- PHYLOG (2016-2020) Certifiability of multi and many-cores architectures
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Conference committee
- PC:
- ERTS 2020, 20222, 2024
- ESREL 2022, 2024
- EDCC 2024
- Local organizer:
- ERTS 2020, 20222, 2024
- PC:
Students
Current PhDs
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Former post-docs
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Education
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2017-2014: PhD thesis at ONERA Toulouse on the development environments and methods for synthesis of predictable and fault tolerant systems . Short abstract: Safety is one of the main guidelines for system design. Designers are in charge to develop architectures that comply with the safety requirements. We propose an automatic hardening method based on the exploration of possible designs to build safe systems. The method uses the state-of-the-art safety analysis methods and SMT solver to propose an efficient resolution of safety driven exploration problem.
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2014--2009: Engineer graduation in automation, electronic and safety critical embedded systems at INSA Toulouse
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2009: High School Diploma received at Lycee Toulouse Lautrec
Experience
- Now - January 2018: Research engineer at ONERA Toulouse, main research topics are:
- the development of model-based safety assessment methods and tools
- the use of formal methods to perform safety assess
- safety-driven architecture optimization relying on IA based methods
- new safety assessment methodologies for autonomous systems
- December 2017--November 2014: PhD thesis at ONERA Toulouse on the development environments and methods for synthesis of predictable and fault tolerant systems .
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February 2014: Master Internship at ONERA Toulouse on the conception of fault tolerant multi periodic longitudinal controller on many core target:
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Survey of classical fault tolerance techniques
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Suggestion of development cycle for controller conception
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Formalization of automatic hardening techniques and implementation of a demonstrator on Matlab with Cecilia OCAS interface
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Application of hardening on longitudinal controller and simulation with SchedMCore tool
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June 2013: Bachelor Internship at MyFox Labege, conception of communication card for ZigBee Home Automation wireless protocol:
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Auto training on ZigBee Home Automation standard
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Hardware and software solution designer (TI CC2530)
Computer skills
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System Modelling: AADL, Matlab, Simulink, UML
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Safety Modelling: Altarica, HipHOPS, GRIF
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Program Languages: C, Java, Scala, Android, SCADE, Lustre , Prelude
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Text-Processing: Word, OpenOffice, Latex
Developments and Tools
The PML Analyzer
The PML analyzer is an open source API providing a simple DSL to build
a description of the architecture of your chip based on the PHYLOG Model Language (PML).
From this representation a set of safety and interference model templates can be generated to perfom safety and
interference analyses of your platform.
The KCR Analyzer Tool
The KCR analyzer is a model-based safety analysis tool for static systems described in the KCR language. This tool is a an implementation of the methods developped in my PhD on "Automatic Synthesis of Fault tolerant Architectures " tutored by Claire Pagetti and Remi Delmas. The manuscript is available here and the presentation slides are available here.
The KCR analyzer provides the following safety analyses using SMT-based and BDD-based techniques.
- computation of reliability
- computation of minimal cutsets (called MCS)
- computation of minimal cardinality of MCS (without computing them)
- check cardinality requirement on MCS (without computing it)
- check system monotony
- check reliability requirement
- solve exploration problem
And the following extra features are provided
- dot export of the Binary Decision Diagram of the structure function
- package management
- syntax highlighting for emacs
Teaching
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Safety assessment of critical systems
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Functional programming
- Introduction to functional programming language Scala 3.0 at ISAE
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Constraint programming
- Introduction to SAT and SMT solver at ENSEEIHT